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A Review on Leakage Current in Low Power Nanoscale VLSI Technology: Challenges and Solution
Kajal and Vijay Kumar Sharma

Advancement in technology increases the expectation of customer in electronics. Better performance with minimum power dissipation is become basic need and low power dissipation is possible when power consumption of very large scale integration (VLSI) device is low. In this review paper, low power Nanoscale VLSI technology is discussed which consider low power consumption in Nanoscale regime. Various challenges face by integrated circuit (IC) designer during the uses of this Nanoscale technology because no one technology is completely satisfied all requirements. Leakage current is main contributor of power dissipation in complementary metal oxide semiconductor (CMOS) technology and number of techniques used to reduce or minimize the subthreshold leakage current and performance of circuit will improved. CMOS digital integrated circuits are most commonly and widely used in VLSI technology. As the need of limit the power consumption in very high density VLSI chips have led to rapid and innovative growth in low power VLSI technology during recent years. Main motivations behind these developments are portable and small size devices which require low power dissipation and high throughput.

Keywords: CMOS logic, nanoscale regime, leakage current, body bias, VLSI

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