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Challenges in Designing Ultra-Low Power VCO
R. A. Walunj, Mohd. Ajmal Kafeel, S. D. Pable and G. K. Kharate

In the era of high component density chips, power consumption has emerged as a forefront design metric. Both power and performance of a system are significantly influenced by the voltage controlled oscillator (VCO) in many analog and digital applications. Lowering the supply voltage is the most effective technique to reduce the power consumption. This paper therefore investigates the challenges in designing the CSVCO at lower voltages. Performance and power consumption of a five stage current starved VCO (CSVCO) is investigated over a wide range of supply voltages. Along with increasing power density, variability poses a significant challenge at lower technology nodes. The analysis of impact of threshold voltage, length, supply voltage, and temperature variation on 3σ/μ (%) delay variability of CSVCO output pulse at different supply voltages ranging from maximum (nominal) voltage in the 32 nm technology (0.9V) to (0.3V) is done independently as well as comprehensively using Monte Carlo SPICE simulations. A non-linear variation of delay variability is observed with various sources of variation over a wide supply voltage range. The results reveal that the process and voltage variations have significant impact on delay variability of CSVCO compared to the temperature variations. It is observed from the simulation results that at the supply voltage (Vdd) of 0.4V, power consumption reduces by 257 times at the cost of increased 3σ/μ delay variability by 8.17% compared to the power consumption and variability at nominal Vdd of 0.9V.The variability is further exacerbated at Vdd=0.3V as seen from the simulation results.

Keywords: Ultra-low power, CSVCO, 3σ/μ (%) delay variability, PVT variations, Monte-Carlo

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