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Calculation of Static Noise Margin for 6T SRAM Cell
Manepally Satya Sai Ganesh and Shyam Akashe

Nowadays, SRAM has become a crucial component of most VLSI chips due to its small access time and high storage density. Static Random Access Memory (SRAM) is designed to provide high speed and low power applications. The SRAM cell is going to exceed 90% of general chip region to fulfil the increased chip functionality demand. The size of SRAM has been reduced, because of its higher density in the System-on-chip (SoC) and other integrated devices, which operates at low power voltage. This leads to significant energy savings, but the stableness and execution of the SRAM circuit are influenced by the continuous decrease in the supply voltage. The minimum supply voltage diminishes the Static Noise Margin whereupon the steadiness of the SRAM cell depends. To enhance the execution of SRAM in nanoscaled technology, there is a need to examine the stability of the cell. The SRAM’s stability can be estimated by static noise margin (SNM). In this paper, we analyzed the SNM based on the traditional butterfly method of 6T SRAM. Therefore, obtained results of 6T SRAM are WSNM of 0.117V, RSNM of 0.520V and HSNM of 0.544V implemented in 90nm Cadence technology with a 0.7V power supply.

Keywords: Static random access memory, Stability, Static noise margin, butterfly method, the low power voltage

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