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Design of Vedic Multiplier via Modified Gate Diffusion Technique for Applications in Digital Signal Processor
Rishu Yadav and Manish Kumar

Vedic mathematics is an ancient technique of mathematics and a brief discussion is made on Vedic mathematics in this paper. Among the various method of Vedic mathematics, Urdhva Tiryagbhyam is discussed in different cases of multiplication. High-speed multiplication is extremely important for the application of the Digital Signal Processor (DSPs), for which the Vedic multiplier is used. This paper presents an improved 4×4 Vedic multiplier using modified GDI via Ripper carry adde, in order to minimize the power dissipation along with the delay of the circuit. The proposed Vedic multiplier using the modified gate diffusion input technique is showing lower power & lesser delay as compared to some of the previous reported works. This proposed work is designed and simulated in 180nm technology by using Mentor Graphics EDA tool

Keywords: Modified gate diffusion input, 4×4 vedic multiplier, gate diffusion input, and ripple carry adder

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