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Ultra-Low Power Hybrid Full Adder Circuit for Digital Signal Processing and Biomedical Applications
Anil Singh, Rahul Mani Upadhyay and Manish Kumar

An ultra-low power 1-bit full adder circuit is proposed in this paper. This circuit consists of three modules that work in integration with each other to generate the output. Module 1 performs the XOR-XNOR operation while module 2 performs the XOR operation and produces the SUM output. Module 3 is a multiplexer circuit that gives the Carry out (Cout) of the adder circuit. The power dissipation of the proposed full adder outperformed with some of previously reported works. The circuit is designed and simulated by using Mentor Graphics simulation tool in 180nm TSMC technology.

Keywords: Full adder, power, hybrid adder, ultra-low power

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