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Optimized Two Stage Low Power Miller Compensated Operational Amplifier with CMOS 180nm Technology
Praween Kumar Sinha, Sumita and Neelam Sharma

An operational amplifier is considered one of the essential electronic devices. This paper mainly concentrates on the optimized design of two-stage CMOS OpAmp for specification taken into account i.e. open-loop gain, phase margin, unity-gain bandwidth, power dissipation, slew rate and others. This work presents a design which operates at ±0.9 supply voltage and simulation process is carried out by using an EDA tool Cadence virtuoso with 180-nm technology. The optimized power dissipation is 45-μwatt with 64.56-dB open-loop gain, 82.87-degree phase margin, 7.7-MHz unity gain bandwidth and output current 130.3-μA.

Keywords: Differential pair, miller compensation, nulling resistor compensation, current efficiency, small-signal analysis

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