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Clock Delayed Dual Keeper Semi Dynamic Inverter Domino Logic Circuit
Manish Deo and Manish Kumar

Power dissipation, delay and power delay product (PDP) are the major design metrics that IC designers have to take care of in any logic circuit design. In this paper, an energy-efficient and fast CMOS domino logic circuit design is proposed. Problems related to subthreshold leakage and contention current have been removed. Clock delayed dual keeper and semi-dynamic inverter are implemented in the proposed circuit technique to improve the performance in terms of power delay product and delay in comparison with other domino logic techniques. Simulation of the logic circuit is performed using Cadence Virtuoso EDA tool in gpdk 180nm CMOS technology.

Keywords: Domino logic, footed domino logic, footless domino logic, clock delayed dual keeper domino logic, Semi dynamic domino logic

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