JAPED Home • Issue Contents

Design of 4:2 Energy-Efficient Compressor Using Hybrid 1-bit Full Adder
Anil Singh and Manish Kumar

This paper present an energy-efficient 4:2 compressor by utilizing hybrid 1-bit full adder which results in low power dissipation and less delay. The proposed circuit also uses only 28 transistors which results in enhancement in its performance. The proposed 4:2 compressor has power dissipation 909.22 pW and delay of 11.60 pS at 1.0V power supply whereas power dissipation of 18.29 nW and delay 1.73 pS

Keywords: Power dissipation, delay, power-delay product, 1-bit full adder

Full Text (IP)