Design and Performance Analysis of Low-Power Hybrid Full Adder Circuit
Rahul Mani Upadhyay and Manish Kumar
A Low-Power one-bit full adder circuit has been proposed in this paper. The main purpose of this paper is to design the XOR-XNOR based full adder circuit which shows better performance and lower power dissipation. The proposed full adder is designed using 14 number of transistors which results in lesser power dissipation. The full adder circuit consists of three modules where each module has its own specific function. Firstly, module-1 generates the XOR and XNOR outputs by taking three binary inputs. The output of module-1 further drives module-2 and module-3. Full output voltage swing, transistor count, and power dissipation are the dominant concern that largely affects the performance of many digital circuits. The work is simulated using Mentor Graphics Eldo simulation tool. The various designs for module-1, module-2 and module-3 are simulated. Then they are all integrated together to yield Sum and Carry outputs of full adder. The proposed adder circuit has an improvement in the power dissipation in comparison with some existing full adder circuits.
Keywords: Full Adder, power dissipation, XOR-XNOR circuit, power delay product