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Implementation of High-Gain Low-Power Two Stage CMOS OP-AMP Employing Current Buffer Compensation in Nanoscale Regime
Pragati Gupta and Shyam Akashe

The operational amplifier is the most versatile and an essential part of many analog and mixed signal system designs. Its performance makes considerable impact on analog systems; therefore, the appropriate design of operational amplifier is very important. This paper presents the design of high-gain low-power two stage CMOS OP-AMP employing current buffer compensation. The current buffer compensation approach has been adopted to enhance the gain-bandwidth product (GBW) with good output swing. To minimize the leakage current, transistor stacking technique is proposed here in which three off-state transistors are stacked on top of each other, consume considerably less leakage current than a single off-state transistor and it works in active and stand-by mode. The designed OP-AMP provides DC gain of 87 dB, enhanced gain-bandwidth product of 190 MHz and an adequate phase margin of 75°. The circuit is operated at the 0.7 V power supply with leakage current of 7.6 pA and power consumption of 19.55 μW only. All the simulations have been performed using Cadence Virtuoso tool in 45 nm technology.

Keywords: CMOS OP-AMP, current buffer, leakage current, low-power, transistor stacking technique, stack effect

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