Performance Analysis of 4 bit Vedic Multiplier for Low Power Computing
Rahul Mani Upadhyay, R. K. Chauhan and Manish Kumar
Multiplier is the most significant computing circuit, as it is used in a variety of calculations. A multiplier is an important component in electronic systems because it allows for multiplication in Digital Signal Processing applications. As a result, a low-power, high-speed multiplier is becoming increasingly necessary. Vedic mathematics improved performance of the multiplier systems used in low-power and high-speed computing. Based on the Urdhva Tiryakbhyam sutra, the architecture of 2 bit and 4 bit multiplier are proposed in this paper. At 45 nm technology Cadence simulator is used for the performance analysis of proposed multipliers. The performance parameters, such as power consumption and delay are determined based on the simulation findings. The proposed 2 bit and 4 bit multiplier operates lower power delay product than the recently designed multiplier.
Keywords: Vedic mathematics, urdhva tiryakbhyam, high speed, low power, multiplier, half adder, full adder