Reduction of Read Power in 10T SRAM Using SVL Technique
Ranu Chaurasia, Akhilesh Kumar Chaudhary and Sudhanshu Verma
In this study, we present a 10T read differential-ended SRAM cell with useful features for low power and stability. This advancement in lower technological nodes is accompanied by number of challenges. In nanometre SRAM design, the consequence of temperature, process variability, and supply voltage on numerous performance characteristics appears to be the most important concern. The proposed 10T SRAM circuit offers a low read power dissipation, higher stability, and better performance. The effect of process parameter variations on key design factors such as the read power of the suggested cell is described and compared to that of a previously SRAM cell. The self-controllable voltage level (SVL) is a series of NMOS transistors that act as resistors and the PMOS transistor functions as a switch to limit leakage current when the transistors switch from active to sleep and vice versa. The reduction in leakage current reduces static power dissipation. The proposed topology allows for differential read and writes operations with single-ended. The conclusions of all simulations such as transistor usage, power dissipation and power delay product and delay of the suggested 10T SRAM cell and SRAM cell are carried out in 45nm CMOS technology using the Cadence virtuoso tool.
Keywords: CMOS logic, SRAM, SVL, memory, low power, high speed