High Speed, Low-Power, Area Efficient Charge-pump Design for PLL Application
Nashra Khalid and Ram Chandra Singh Chauhan
Some significant non-idealities, including current mismatch, phase noise, and reference spur, have been observed as the design of charge-pump (CP) circuit has advanced. Lock-in time is regarded as one of the crucial characteristics of an efficient CP design but to achieve it always poses an unsolved problem for prospective use in high-speed mobile communication. This paper presents a simple power efficient drain switching based charge-pump incorporating an op-amp. Drain switching topology enables results in faster switching speed and the use of moderate gain providing op-amp reduces the current mismatch. Power consumption of the design is only 125.58 μW. The key features of this design is low current mismatch which is only 0.71% and fast lock-in time of merely 5.15ns. The proposed circuit is simulated using CADENCE VIRTUOSO platform using 90nm CMOS technology at a supply voltage of 1.2V and the operating frequency of 1.25GHz. The noise response of the circuit is also good with phase noise of -101.24 dBc/Hz @10MHz which is much better than the predefined circuits. This makes it suitable to be used in Phase-locked-loop (PLL) systems required for high-speed mobile communication applications. Monte Carlo and process corner analysis is done to validate the performance of novel charge-pump circuit.
Keywords: Phase-locked-loop, charge-pump, current mismatch ,phase noise, low power, high speed