Novel Quantum Adder Circuit Design Using CNOT Gate
Joy Bhattacherjee and Arpan Deyasi
The necessity of designing quantum circuits has increased with the development of effective quantum algorithms and methodological developments. The two major outcome that is always desired to achieve in designing a quantum circuit are to reduce the number of gates and also of gate levels. Owing to special features of quantum decoherence, a decrease in gate count and the number of circuit levels minimizes errors which is reflected by probability measurement of output for pre-defined input set. The present paper deals with novel half adder and full adder circuits implemented using CNOT and CCNOT quantum gates. Probabilistic analysis is carried out for each specific case, and result exhibits significant improvement over less area consumption compared to published findings. Results are significant for developing complex combinational circuits using CNOT and CCNOT gates.
Keywords: Quantum adder, CNOT gate, CCNOT gate, Probability output, Quantum circuit simulation