p. 81-97
Study and Comparison of 45nm CMOS One-Bit Full Adders Based on Energy-Delay Trade-offs
N. Ramanjaneyulu, P. Chandra Sekhar, E. Chandralekha, Y. Jaya Sreenivas Reddy, D. Hanuruthkumar and P. Siddhartha
Abstract
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p. 99-120
High-Speed VPAC with Low Hardware Complexity for Efficient ADPLL Applications
Sehmi Saad, Afef Kchaou, Aymen Ben Hammadi and Hatem Garrab
Abstract
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p. 121-137
A Study of PVT Analysis of Various CMOS Current Mirror Configurations in 45nm Technology
Ningampalli Ramanjaneyulu, Donti Satyanarayana, Sari Mohan Das, Yerraboina Sreenivasulu, V.N.V. Satya Prakash and Mohan Dholvan
Abstract
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p. 139-155
Implementation of Energy and EDP Efficient Full Adder Circuits for Computing Systems
Ramaswamy T, S. P. V. Subba Rao, A. Saketh, B. Sathwik Goud, K. Varshith Reddy and Srinivasulu Gundala
Abstract
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p. 157-168
A Signal Processing Framework for Hindi Digit Recognition with Kaldi ASR
Prashant Upadhyay, Anupam Vyas Atul Makraiya and Nishtha Vyas
Abstract
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