A Study of PVT Analysis of Various CMOS Current Mirror Configurations in 45nm Technology
Ningampalli Ramanjaneyulu, Donti Satyanarayana, Sari Mohan Das, Yerraboina Sreenivasulu, V.N.V. Satya Prakash and Mohan Dholvan
Current mirror is an essential structure in signal design for mixed and analog circuits, serving to gauge their efficiency based on their properties. It’s the current amplifier with unity gain that produces output current in proportion to the input current through its output node with high impedance. It also maintains constant current regardless of a load. Current mirrors can be utilized as Direct Current (DC) sources and current amplifiers, active loads and for biasing in many mixed signal and analog circuits, such as operational amplifiers, transconductance amplifiers and operational amplifying mirrors. Over the past two decades, the design of current mirror circuits faces several limitations. The limitations are, threshold voltage is varied from 50 to 100mV for wafer to wafer, Metal Oxide Semiconductor (MOS) transistors (μn and μp) are temperature dependent, current mirror circuits place the transistors in same length due to which transistor sizing problem occurs. Important factors that influence performance of current mirror are: Accuracy, input resistance, output resistance and bandwidth. In this paper, 5 different types of current mirror circuits will be simulated by using Cadence-Virtuoso tool using CMOS 45nm technology. Current mirrors circuits are simulated in unique temperatures like 0°C (SS-Slow-Slow), 15°C (SF-Slow-Fast), 27°C (Normal Temperature), 55°C (FS-Fast-Slow), 65°C (FF-Fast-Fast). A comparative Process Voltage Temperature (PVT) analysis of various circuits can be investigated in terms of accuracy, input and output resistance and is suspected to perform better in terms of power consumption, output
resistance.
Keywords: CMos, current mirror, low voltage circuits, input and output resist