Implementation of Energy and EDP Efficient Full Adder Circuits for Computing Systems
Ramaswamy T, S. P. V. Subba Rao, A. Saketh, B. Sathwik Goud, K. Varshith Reddy and Srinivasulu Gundala
Addition holds considerable significance as an essential building block of mathematical computation and it is the primary element for synthesizing multiple operations and high-performance adders play an integral role in developing applications-specific integrated circuits (ASICs) for multiplication. Recently, there has been a surge in interest to GDI logic circuits, as a method to cut down on energy usage; they offer a unique approach to design low-power circuits that can reduce the power consumption as well as the propagation delay and the physical size of electronic circuits. This paper highlights an efficient GDI 1-bit full adder circuits with exceptionally low energy consumption. Full adders are efficiently implemented through full-throttle OR, AND, and XOR gates and their performance has seen substantial enhancements as a result of these modifications. Simulations were run for circuit designs using cadence and virtuoso tools using CMOS 45nm technology with a supply voltage of One Volts. The 1-bit adder cells proposed here are compared with different fundamental adders based on operation speed, power consumption, and energy (PDP). Adder circuits with full swing logics have the capacity to attain momentous savings in terms of delays and energy use with respect to the standard 1-bit C-CMOS full adders and former counterpart.
Keywords: CMOS, computing systems, delay, DSP processors, full adder, low power