Study and Comparison of 45nm CMOS One-Bit Full Adders Based on Energy-Delay Trade-offs
N. Ramanjaneyulu, P. Chandra Sekhar, E. Chandralekha, Y. Jaya Sreenivas Reddy, D. Hanuruthkumar and P. Siddhartha
The rising demand for energy-efficient digital circuits has intensified interest in optimizing arithmetic units like full adders. This study focuses on evaluating the energy-delay trade-offs of six different 1-bit full adder topologies implemented using 45nm CMOS technology, namely, Conventional Mirror CMOS (CMC), Complementary Pass Transistor Logic (CPL), Low Power (LP), Transmission Gate through Driving Capability (TGDC), New Hybrid Pass Static CMOS (NHPSC), and Dual Rail Domino (DRD). Using the Cadence simulation tool, we analyze power dissipation and propagation delay under identical operating conditions. The results are mapped onto an energy-delay trade-off plot, offering a visual comparison of each adder’s efficiency and speed. The findings reveal that the DRD topology is the most energy-efficient, consuming only 16.30% of the total energy, whereas NHPSC is the least efficient, consuming 83.82% of the energy. Regarding speed, the CMC topology is the fastest. CMC topology has the lowest delay of 21.32 percent, while NHPSC is the slowest with the longest delay that is 73.36%. NHPSC full adders took up 78% less space than DRD designs which took up 624.23 um2. This research provides useful insight into strengths and weaknesses of various designs for full adders that enable circuit designers to make informed choices according to specific application needs.
Keywords: Full Adders, CMOS, Energy-Delay Trade-off, Power Dissipation, Propagation Delay