Study and Implementations of Adder Circuits for Energy and EDP Efficient Computing Systems
Ramaswamy T, S. P. V. Subba Rao, Mohammed Mahaboob Basha, Alakuntla Jithender, Pamidikonda Nachiketh and Vatlam Dheeraj Kumar
Addition plays a vital role in mathematical calculation and serves as the primary element to synthesize multiple operations, while high-performance adders play an integral part in developing applications-specific integrated circuits (ASICs) for multiplication. This article describes an energy efficient one-bit adder by way of low voltage and high performance internal logic circuits, enabling it to achieve a reduced energy (Power Delay Product) and EDP. Furthermore, custom XNOR and XOR gates, two crucial components, are also described. Simulation of planned circuits was carried out with Cadence Virtuoso software using 45 nanometer CMOS technology and voltage of 0.4 and 0.9 Volts. One-bit Adders from various trendy adder designs were then evaluated on power, speed, and power consumption (PDP) and EDP. Adder strategies using altered internal entity cells have shown to significantly decrease delay and energy consumption and EDP compared to standard “C-CMOS” 1-bit full adders and counter components, by more than 30 percent correspondingly.
Keywords: Low power, high performance, energy and EDP efficient, various full adders