Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process
T. Jayachandra Prasad, M. Chennakesavulu, Bojja Ramesh Reddy, Vadde Seetharama Rao and Shaik Kashif Hussain
Most applications especially those in scientific computing and finance, require decimal arithmetic. Conventional binary hardware necessitates conversions between binary and decimal as well as between decimal and binary, which results in errors that cost money. Using complementary metal-oxide semiconductor (Complementary MOS) technology, the research reported here proposes decimal addition circuits. The circuits examine several BCD arithmetic unit designs and minimize errors brought on by decimal-binary conversions. Using contemporary binary adders, five distinct BCD arithmetic units—Conventional, Modified, Compact, Novel, and High-Speed 4-bit Carry Look-Ahead (CLA) architectures—are presented. The suitability of each architecture for BCD addition is assessed through comparison. The suggested circuits’ functionality is simulated and confirmed using CADENCE simulator software. The performance over 45nm technology is evaluated using the metrics of power-delay product (PDP), latency, and power consumption. According on the experimental findings, the suggested decimal adder outperforms current models. The suggested adder, for instance, yields a PDP of 23.798 fJ for 4-digit operands, whereas other efforts yield more energy consumption in comparison to the adders in the literature.
Keywords: BCD arithmetic units, complementary MOS, carry look-ahead adder