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Crosstalk Reduction by Voltage Scaling in Global VLSI Interconnects
B.K. Kaushik, S. Sarkar, R.P. Agarwal and R.C. Joshi

Voltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product (PDP). Therefore, their lies an optimized supply voltage where-in power dissipation and propagation delay can be optimized. Many of the previous researchers have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. It is quite encouraging to observe that irrespective of technology node used, an optimized voltage scaling reduces normalized crosstalk level. This paper shows simulation results for crosstalk reduction in different nano-sized CMOS driven RLC-modeled interconnects.

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