A Novel Design of High-Performance CNTFET-Based Full Adder Using Optimized XORXNOR Cell
Uma Sharma and Mansi Jhamb
With the growing limitations of traditional CMOS technology at nanoscale dimensions, Carbon Nanotube Field Effect Transistors (CNTFETs) have gained attention as a promising substitute, owing to their superior charge transport efficiency, structural strength, and thermal stability. This work introduces an innovative design approach for realizing a high-speed, energy-efficient full adder using CNTFET technology. The architecture incorporates a custom-developed XOR-XNOR logic unit featuring a grounded keeper technique to ensure signal integrity and robust operation. The proposed designs of CNFET based XOR-XNOR cell and full adder are simulated using HSPICE tool at 32nm CNTFET Stanford technology model and aims to minimize power consumption, delay and area of the circuit, and take advantage of the unique properties of CNTFETs. Additionally, the proposed CNTFET-XOR/XNOR cell design is subjected to process, voltage, and temperature (PVT) variations to evaluate its stability. The outcomes demonstrate that, in comparison to current state-of-the-art designs, the suggested design is more resilient. In this work, a XOR-XNOR cell is used to implement a 1-bit full adder as an application. This makes the proposed design acceptable for high-performance integrated circuits. The proposed full adder design demonstrates a significant reduction in power-delay product (PDP) in comparison to the existing CNTFET-based full adders, achieving improvements ranging from 16.71% to 81.07%.
Keywords: XOR-XNOR cell, full adder, grounded keeper circuit, CNTFET, PDP