Implementation of Energy and EDP Efficient Adder Circuits at Sub Threshold Regime for Signal Processing Applications
Challa Pamuleti, S M Shamsheer Daula, Srinivasulu Gundala, K. Madhuri and P.M. Ashok Kumar
In a lot of latest high-speed designs, the leakage current component which consumes power is similar or more than that of switching current or in other way dynamic component. The reports point towards that 70% or more proportion of entire power utilization is caused by the seepage of transistors. The fraction of leakage will rise as technology advances unless efficient methods are developed to control leakage. This article concentrates on optimizing circuits and designing strategies for automation to achieve this aim. The initial part of the article offers an overview of the low threshold NMOS transistors combined with NAND and NOR logic gates to achieve reduced power consumption and delays. Modified universal gates serve as essential blocks in designing this proposed adder cell. The second section of the article outlines various ways to optimize circuits for controlling the leakage current so as to achieve high speed 1-bit full adders created with. Simulations were carried out using Cadence Virtuoso with 45nm CMOS technology at 1 Volt supply voltage. Projected universal gates and one-bit adders are compared against basic NAND/NOR gates and with conventional adders for computing purposes. The projected adder designs through customized NAND/NOR logic styles attain remarkable saving in terms of sum and carry delay which is about more than 15.22 % at the cost of 8.67% average power consumption when compared by means of conventional designs.
Keywords: CMOS, delay, leakage power, NAND and NOR gates, adders, energy efficient