Performance Optimization of Super Scalar Level Shifter for High Performance Computing Applications
K.M. Hemambaran, Dholvan Mohan, Srinivasulu Gundala, Mohammed Mahaboob Basha and M. Rohitha
In recent ICs, the use of sub-threshold power management has become a necessity due to energy-efficiency. Level Shifters (LSs) are used to exchange signals between different voltage domains. They ensure the reliability of ICs and signal integrity. The low-power LS shown is a combination of multi-Vt, diode connected leakage aware, load balancing design, allowing for up shift or down-shifts. In this article the Performance optimization of Super Scalar level Shifter for High performance Computing Applications (SSLS) is proposed. SSLS integrates multi-Vt, and load-balancing inverter for optimization of performance metrics. The schematic structure is capable of converting voltages high into low as well. It is the design architecture that has the least silicon area. The proposed design is implemented using 55 nm-CMOS. This LS is capable of converting voltages from 0.30 V to 1.30 V with a 2.01 nW dynamic power. The LS has a propagation area of 7.660 um 2 and a delay of 90 ps.
Keywords: Computing applications, level shifter, load balancing, low power, multi-Vt