AI-Driven Pareto-Optimal Design Exploration and Performance Analysis of Low Power Data-Centric VLSI Systems
Nancherla Kavitha and S. M. Shamsheer Daula
Modern low-power VLSI architectures face increasing energy challenges due to data-intensive workloads in IoT and edge-AI systems. A data-centric power modeling approach was developed to capture switching activity, memory hierarchy behaviour, and on-chip data movement, enabling accurate estimation of energy beyond compute-only analysis. To accelerate power–performance estimation across large architectural design spaces, a unified graph-based hardware representation and a Graph Neural Network (GNN) surrogate were built to predict Power, Performance, and Area (PPA) with sign-off–level accuracy while avoiding costly full EDA simulations.Building on this foundation, this work introduces a reinforcement-learning–driven multi-objective Design Space Exploration (DSE) framework that automatically identifies Pareto-optimal VLSI configurations. The GNN surrogate provides rapid PPA evaluation, and uncertainty-based pruning eliminates low-value candidates, significantly reducing the number of PrimeTime-PX simulations. A non-dominated sorting mechanism extracts the final Pareto frontier while optimizing for minimum power, reduced latency, and area constraints. Experimental evaluation on CNN, RNN, FFT, and DNN workloads shows an average 32% reduction in total power, 35% lower energy per inference, 17% latency improvement, and up to 75% fewer full simulations.
Keywords: Low-Power VLSI, Data-Centric Design, Pareto Optimization, Reinforcement Learning, Design Space Exploration, Surrogate Modeling, PrimeTime PX, IoT Hardware, Memory Hierarchy, Interconnect Power