Performance Analysis of Different CNTFET Based Full Adder Cells at Nano Scale Regime for Energy Efficient Computing Systems
Dega Srinivasulu Reddy, Challa Pamuleti, Sari Mohan Das, O. Hemakesavulu and V.N.V. Satya Prakash
As silicon-based CMOS technology enters nanoscale territory and approaches its physical limit, one of the more significant advanced transistor technologies that have advanced beyond Moore’s Law is thought to be Carbon Nanotube Field-effect Transistors (CNTFETs). Carbon nanotubes (CNT) have been recognized as a modern new technology which could tackle some of the weaknesses in CMOS without impacting performance or trustworthiness. A CNTFET Gate Diffusion Input (GDI) hybrid adder is a type of electronic circuit designed to perform addition using CNTFETs and combining the GDI technique with a hybrid CMOS logic style to achieve low power consumption and high speed. These circuits are also developed for approximate computing, which is beneficial for applications like image processing by trading off some accuracy for significant reductions in area, power, and delay. Furthermore, hundreds of nanowires may be added into its conductivity channels in order to increase current transport capabilities with lower supply voltages and thus providing a foundation for designing ultra-large scale analog/digital logic circuits on nanoscale levels.
Keywords: Near threshold, CNTFET, adder circuits, CMOS, power, energy, EDP