Performance Analysis of Various One Bit Adder Based Multipliers at Nanoscale Regime for Energy Efficient Computing Applications
C. Padma, G. Amjad Khan, Rajesh Thumm, G. Chandraiah, K. Deepthi and Nagireddy Srinivasa Reddy
In a lot of latest high-speed designs, the reports point towards that 70% or more proportion of entire power utilization is caused by the leakage of transistors while moving towards near threshold computing. Gate diffusion input (GDI), an innovative technique of low-power digital logic circuit design, is presented here. This approach can reduce power consumption, propagation delays and digital circuit size whilst maintaining simple logic style. In this paper, area and energy efficient multipliers have been created through hybridization of PTL and GDI techniques within adder designs. The implemented adders were then compared with different CMOS, CMOS along with TG (24T) and 10T based 1-bit adder designs. A PTL logic based XOR-XNOR module equipped with GDI was deployed to optimize area utilization while increasing energy utilization, then contrasted against some existing adder designs. Numerous multiplier circuits have been implemented by using this hybrid adder in a combination of different design styles. The GDI based hybrid adder is energy efficient and its multipliers are also achieved the better results when compared with other counter parts.
Keywords: CMOS, one bit adders, delay, power, energy efficient multipliers