Dielectric Engineering Effects on Threshold Voltage Roll-off, Subthreshold Swing and DIBL in Junctionless Double Gate MOSFET for Nanoscale Applications
Koyena Bhowmick, Pampa Debnath and Arpan Deyasi
Roll-off of threshold voltage for junctionless accumulation mode double gate MOSFET is analytically investigated by considering high-K low-K dielectric stack at both the sides of the device. Minimum surface potential is computed from the solution of Poisson’s equation, and thereafter threshold voltage is roll-off is estimated assuming constant doping in both source and channel regions. A vis-a-vis analysis with junction devices exhibits 96.51% and 98.58% improvement of roll-off voltage when compared with high-K and low-K dielectrics respectively. Moreover, 75.8% improvement of result is obtained when compared with published result of similar structures, which speaks about extremely low leakage current and thereby, power consumption. While increasing dielectric thickness impairs device performance and raises DIBL by roughly 60-80% in junctionless double-gate MOSFETs, increasing channel length generally improves electrostatic control by lowering subthreshold swing and DIBL by about 40-60%. Result establishes novelty of the present calculation, and thereby justifies the work.
Keywords: Junctionless DG MOSFET, threshold voltage roll-off, gate oxide thickness, doping concentration, substrate thickness, DIBL