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Design and Implementation of a Configurable Real-Time FPGA-Based TM-CFAR Processor for Radar Target Detection
Abdullah M. Alsuwailem, Saleh A. Alshebeili and Mohammed Alamar

The signal returns from radar targets are usually buried in thermal noise and clutter. Target detection is commonly performed by comparing radar returns to an adaptive threshold such that a constant false alarm rate (CFAR) is maintained. The threshold in a CFAR detector is set on a cell by cell basis according to the estimated noise/clutter power, which is determined by processing a group of reference cells surrounding the cell under investigation. In this paper, a configurable Field Programmable GateArray (FPGA)-based hardware architecture forTrimmed Mean (TM)-CFAR processor for radar target detection is presented. The proposed processor is designed, implemented, and tested using Stratix FPGA chip (EP2S60F1020C4 device). The system has the advantages of being simple, fast, and flexible with low development cost. For a reference window of length 16 cells, the experimental results carried out using Altera development kit showed that the proposed processor works properly with a processing speed up to 100 MHz.

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