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ΔIDDQ Testing of CMOS Data Converters+
S. Yellampalli and A. Srivastava

This paper presents a difference in quiescent current (ΔIDDQ ) testing of CMOS data converter circuits designed in submicron CMOS process. The built-in current sensor (BICS) follows the method of capacitive voltage discharge across the circuit under test. The faults simulating manufacturing defects such as shorts in MOSFETs are injected using fault injection transistors with resistors in series combined with fault equivalence in 12-bit ADC and 12-bit DAC designed in 0.5 μm n-well CMOS process for 2.5 V operations. The logic Scan-Path method is also used for digital CMOS part of data converters testing in combination with the ΔIDDQ testing for introducing a large number of faults. The combined methods have allowed testing 520 introduced faults in 12-bit ADC, 60 faults in 12-bit DAC with at least 90% fault coverage from post-layout simulation experiments. ADC and DAC fabricated designs were also tested experimentally for a small sub-set of five injected faults using fault injection transistors due to die size and input/output pin limitations. Experimentally measured results have detected four injected faults in both circuits and are in close agreement with the corresponding simulation results. ΔIDDQ test method has taken into consideration effects of process variations through process transconductance and threshold voltage parameters of the MOSFET.

Keywords: Built-in current sensors (BICS); ΔIDDQ testing; CMOS analog/mixedsignal IC testing; CMOS data converter testing, ADC; DAC

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