JAPED HomeIssue Contents

FPGA-Based Design and Realization of Fixed and Floating Point Matrix Multipliers: A Review
Syed Manzoor Qasim, Shuja Ahmad Abbasi and Bandar Almashary

Matrix multiplication is a computationally-intensive and fundamental matrix operation in many algorithms used in scientific computations. It serves as the basic building block for many signal, image processing, graphics and robotic applications. To improve the performance of these applications, a high performance matrix multiplier is required. Traditionally, matrix multiplication operation is either realized as software running on fast processors or on dedicated hardware (Application Specific Integrated Circuits (ASICs)). Software based matrix multiplication is slow and can become a bottleneck in the overall system operation. However, hardware (Field Programmable Gate Array (FPGA)) based design of matrix multiplier provides a significant speed-up in computation time and flexibility as compared to software and ASIC based approaches respectively. In this paper, we present a study of reported work from past ten years, covering various aspects of FPGA-based design and realization of matrix multipliers. A study of fixed and floating-point designs of matrix multiplier is also presented. Finally, some applications where matrix multiplication is the core operation are highlighted and discussed.

Keyword: Field Programmable Gate Array (FPGA), Hardware Realization, Matrix Multiplier, Review.

Full Text (IP)