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A Comparative Analysis of Voltage-Scaled Two Operand Binary Adders
Rajeevan Chandel, Devesh P. Singh, R. Banta, R. Karan and P. Bhatt

Adders are one of the most important circuits in VLSI design. Addition is used in most of the arithmetic operations. This paper compares nine different configurations of two Operand Binary Adders. Both 8-bit and 16-bit adders are compared. Comparison is based on various performance measures viz., delay, area and power dissipation. For portable battery operated miniaturized devices, voltage-scaling is an ideal option for enhancing the battery life; hence the study also includes the effect of voltage-scaling on adder circuits under consideration. Power-Delay-Number of transistors-Product (PDNP) criteria is used as a figure of merit for performance analysis of adder circuits in the present study. The analysis shows that Brent-Kung Adder has the lowest PDNP. PDNP shows a decrease of nearly 2 times at the scaled voltage thereby showing a significant importance of voltage-scaling in adder circuits under study. Different Adders show different tradeoffs between the various performance measures. MEMS Pro Tanner EDA Tools are used for the present simulation study.

Keywords: Adders, voltage-scaling, area, delay, power dissipation.

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