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Optimal Conditions for Ultra Low Power Digital Circuits
Prasad D. Khandekar and Shaila Subbaraman

Increasing demands to improve VLSI digital system performance fueled the necessity of low-power design methodology. Historically, the system performance had been synonymous with circuit speed and processing power. But recently, area and time are not the only parameters to be considered while deciding the system performance. Power consumption is yet another metric. Adiabatic logic, which works on the principle of Energy Recovery, is proving to be an emerging low power approach in low power design. This paper will help in selecting the maximum frequency, device size and the fan-out to design 2:1 multiplexer circuit for ultra-low power application. The outcome of this research work will provide guidelines for designing ultra-low power circuits using adiabatic technique. All the circuits are designed using cell based design approach and 180 μm device size in Cadence.

Keywords: Adiabatic, Energy-Recovery, PAL, CAL.

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