Design of a High Speed, Low Power and Area Efficient MAC for VLSI-DSP Chip
Neha Jain, B. K. Kaushik, Bhavana Jharia and R. P. Agarwal
The work presented in this paper deals with design and transistor level implementation of a high speed, low power, area efficient MAC unit. Multiplier Accumulator (MAC) is an integral unit of almost every DSP chip. MAC is highly responsible for efficient implementation of DSP applications such as digital filtering, speech processing, video coding, CDMA and many others. The MAC architecture is based on generation of partial products using Modified Booth algorithm and then construction of Binary trees using 4–2 compressor circuits. Innovative logic design style such as Complementary Pass Transistor Logic (CPL) and Complementary Pass Transistor Logic-Transmission Gate (CPL-TG) are used for implementation of Booth encoder and 4–2 compressor. A 16-bit MAC circuit using the proposed architecture is prototyped in 0.35 micron CMOS technology. In comparison to published results, a remarkable improvement in speed of around 1.5 times and reduction in silicon area, at a trade of marginal increase in power dissipation is achieved by the proposed design. These positive results will be more pronounced in reduced transistor feature size, which suggest the development of new generation MAC that may be benefited from proposed logic design. The delay and power dissipation performance can be further improved by proper design of interconnects and optimal repeater insertion. This paper presents the design details.
Keywords: Multiplier-Accumulator, Carry Select Adder, Add-One Circuit.