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Low Voltage CMOS Differential Difference Current Conveyor and Its Testability
Parshotam S. Manhas and K. Pal

This paper presents a FGMOS-based CMOS realization of differential difference current conveyor (DDCC) at low voltage levels. In analog circuit design the FGMOS transistors are very often used in low voltage circuits, where the reduction obtained in the transistor apparent threshold voltage is of great importance. The circuit provides very high input impedance at its Y-terminals, low output impedance at X-terminal and high impedance at Z-terminals and consumes less power. This circuit is a powerful building block, similar to a differential difference amplifier (DDA) at the input side and a CCII at the output side. Consequently one is able to design DDCC- based circuits which combine the properties of both DDAs, such as high input impedance, low output impedance and low component count, with the higher usable gain, accuracy and bandwidth of the CCII. The popular current conveyors, such as, CCII, CCIII, ICCII, and DVCCII can also be directly realized by using DDCC. The testability of this circuit is further confirmed by using it in the filter topology. The circuit behavior has been verified using PSpice simulations for 0.5μm technology and indicates the excellent performance.

Keywords: low-voltage analog circuits, DDCC, FGMOS realization.

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