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Analytical Modeling of Threshold Voltage of Stacked Triple-Material-Gate (TMG) Strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs
Abirmoya Santra, Mirgender Kumar, Sarvesh Dubey, Sattabrata Jit and Pramod Kumar Tiwari

The present paper deals with the modeling of threshold voltage of the triple-material-gate (TMG) strained-Si (s-Si) on Silicon-Germaniumon- Insulator (SGOI) MOSFETs. The gate is stacked with high dielectric constant (k) material and interfacial silicon dioxide layer. The threshold voltage expression is obtained from surface potential which is derived by solving the 2-D Poisson’s equation by using the parabolic approximation method. The impact of various device parameters like the gate oxide thickness and strained-Si thicknesses, high permittivity materials, Ge mole fraction, channel doping and gate length ratio on surface potential, threshold voltage and drain induced barrier lowering (DIBL) has been extensively studied. Through the present study, the device designers will found various degrees of freedoms to get desired performance. The developed analytical model results are verified by numerical simulation data from ATLAS™, a 2D device simulator from Silvaco.

Keywords: Short-channel effects (SCEs), Triple-material-gate (TMG), Hotcarrier effects (HCEs), Drain Induced Barrier Lowering (DIBL), High-k materials

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