Fault Tolerant QCA Logic Circuit Using Genetic Algorithm Under Regular Clocking Scheme
Amit Kumar Pramanik, Jayanta Pal, Sunidhi Priyadarshini and Bibhash Sen
Quantum-dot Cellular Automata (QCA) is one of the approaches to synthesizing circuits with high density and low power dissipation to conquer pitfalls of CMOS. In QCA, the performance relies on the primitive gate count, which can be optimized by minimizing the gate count. On the other hand, proper cell layout, scalability, and reliability of the circuit can be ensured with the utilization of a regular clocking scheme. The impact of Genetic Algorithm (GA) in gate count optimization on regular clock based QCA circuits is analyzed in this research. Few multi-output boolean functions are realized using an elitism-based method considering USE and RES clocking schemes. A performance study with respect to energy consumption, QCA cost, and fault tolerance are analyzed in this work. Circuits are realized in QCADesigner. QCAPro and QCADesignerE are used for energy dissipation analysis, whereas HDLQ is used for fault tolerance analysis. The result witnessed an oscillating observation in the performance of the USE and RES clocking schemes.
Keywords: QCA, genetic algorithm, regular clocking, power analysis, fault tolerance, QCAPro, QCADesignerE, HDLQ