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Low-Power Voltage Comparator Circuit for CMOS Quaternary Logic
Yongjian Brandon Guo and K. Wayne Current

This paper presents a new low-power comparator circuit for use in voltage-mode CMOS multiple-valued logic (MVL) circuits. Existing MVL comparator circuits require either DC power and/or clocking power. The circuit presented in this paper uses static logic and requires no static power. It has been simulated with HSPICE using the transistor model parameter values of the TSMC T14A_2P4M 0.35-µm n-well CMOS technology. With a 3.3-volt power supply, simulations show that the proposed quaternary comparator consumes 0.38 nW total average static power and has a worst-case average critical path propagation delay of 6.4 ns. This proposed new circuit has worst case delay and layout area comparable to previously presented static quaternary logic voltage comparator circuits designed with the same technology and power supply, and power dissipation about 5 orders of magnitude less than those circuits. Also presented are simulations using the 0.35 µm technology model parameter values with an optional thick oxide and a power supply of 5 V, and simulations using the model parameter values of a 1.2-µm n-well CMOS technology and a 5 V power supply. Power, area, and speed for comparators designed in these technologies are discussed.

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