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Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis
Masanori Natsui, Naofumi Homma, Takafumi Aoki, and Tatsuo Higuchi

This paper presents an efficient graph-based evolutionary optimization technique, called Evolutionary Graph Generation (EGG), for automated circuit synthesis. An important feature of EGG is its capability to optimize general graph structures directly instead of encoding the structures into indirect representations, such as bit strings and trees. The EGG system can be applied to various circuit optimization problems at different levels of abstraction. In this paper, we demonstrate the potential capability of EGG in designing multiple-valued logic circuits with different levels of abstraction. In general, the practical design of multiple-valued logic circuits can be divided into (i) the gate-level logic design using primitive logic gates whose functions are defined by logical expressions and (ii) the transistor-level precise circuit design of each primitive logic gate realizing analog transfer characteristics. Design examples discussed in this paper include (i) the gate-level design of multiple-valued current-mode logic circuits for redundant arithmetic and (ii) the transistor-level design of high-performance current mirrors to be used as basic components in current-mode logic.

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