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Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic – Device Scaling and Future Prospects
Katsuhiko Degawa, Takafumi Aoki, and Tatsuo Higuchi

This paper presents prototype design and fabrication of Field-Programmable Digital Filter (FPDF) LSIs, which employ carrypropagation-free redundant arithmetic algorithms for faster operation and Multiple-Valued Current-Mode Logic (MV-CML) for high-density low-power implementation. The original contribution of this paper is to evaluate, through actual chip fabrication, the potential impacts of MV-CML circuit technology on hardware reduction in programmable LSIs. The prototype FPDF fabrication with 0.6mm and 0.35mm CMOS technology demonstrates that the chip area and power consumption can be significantly reduced, compared with the standard binary logic implementation. Major problems associated with device scaling are also analyzed to discuss future prospects of MV-CML technology.

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