Introduction to the Special Issue: Nano MVL Structures
Svetlana N. Yanushkevich and Vlad P. Shmerko
The fundamental objective of nanotechnology is to model, simulate, design and manufacture nanostructures and nanodevices with extraordinary properties and assemble them economically into a working system with revolutionary functional capabilities. This special issue on Nano MVL Structures represents a collection of selected papers devoted to applying known computing paradigms to nanotechnology, or to developing the new ones:
Design of a Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors by K. Degawa, T. Aoki, T. Higuchi, H. Inokawa, and Y. Takahashi.
Minimization of Ternary Reversible Logic Cascades Using a Universal Subset of Generalized Ternary Gates by E. Curtis and M. Perkowski.
Multiple Path Switching Device utilizing Size-controlled Nano-Schottky Wrap Gates for MDD-based Logic Circuits by Seiya Kasai, Tatsuya Nakamura and Yuta Shiratori.
The other two papers, initially submitted and accepted for this special issue, On Universality of General Reversible Multiple-Valued Logic Gates by P. Kerntopf, M. A. Perkowski, and M. H. A. Khan, and Synthesis of Quantum Multiple-Valued Circuits by D. M. Miller, D. Maslov, and G. W. Dueck, were published in Volume 12, Number 5-6, 2006 of this Journal.
The guest editors wish to gratefully acknowledge the authors, as well as the important support given us by our reviewers. They spent their valuable time and have put an incredible amount of their valuable time and effort into reviewing the papers.