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Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits
Nobuaki Okada and Michitaka Kameyama

A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a Series-Gating Differential-Pair Circuit (SGDPC) having only one current source. A4-valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.

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