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Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language
Naofumi Homma, Yuki Watanabe, Katsuhiko Degawa, Takafumi Aoki and Tatsuo Higuchi

This paper proposes a high-level design method of multiple-valued arithmetic circuits. The proposed method uses a cell-based approach with a dedicated hardware description language called ARITH. By using ARITH, we can describe and verify any binary/multiple-valued arithmetic circuits in a formal manner. The ARITH description can be transformed into a technology-dependent netlist in binary/multiple-valued fused logic. The process of transforming the netlist into a physical layout pattern is automatically performed by an off-the-shelf place-and-route tool. In this paper, we present a specific cell library containing a multiple-valued signed digit adder and its related circuits with a 0.35μm CMOS technology, and demonstrate that the proposed method can synthesize a 32 × 32-bit parallel multiplier in multiple-valued current-mode logic from an ARITH description.

Keywords: Multiple-valued logic, arithmetic circuits, circuit design, hardware description language, current mode logic.

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