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A Single Parity-Check Digit for One Trit Error Detection in Ternary Communication Systems: Gate-Level and Transistor-Level Designs
Reza Faghih Mirzaee, Mahya Sam Daliri, Keivan Navi and Nader Bagherzadeh

Error detection is a very important subject for all communication systems, including those that use Multiple-Valued Logic (MVL). Parity-check code is a well-known, low-cost, and effective approach. One way of adding parity-check digits in ternary logic is to compute both 1’s and 2’s parities separately. In this way, two redundant ternary digits (two trits) are appended to a block of data (dataword). This paper suggests another method which uses only a single parity digit with the same minimum Hamming distance of two. Therefore, one trit error is detectable for both methods. Not only does the transmission rate of actual information increase by reducing redundancy, but the proposed ternary operator also functions faster and consumes less power when it comes to transistor-level implementation. HSPICE simulation based on 32nm Carbon Nanotube FET (CNFET) technology demonstrates 21.7% higher performance in terms of energy consumption for the proposed operator (TPC) over the ones that generate 1’s and 2’s parities concurrently (EP1 and EP2).

Keywords: Ternary logic, MVL communication system, parity-check, error detection, CNFET, transistor-level circuitry

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