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Counter Tree Diagrams: A Unified Representation of Fast Addition Algorithms
Jun Sakiyama, Takafumi Aoki and Tatsuo Higuchi

This paper proposes a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs), which are useful for designing high-performance arithmetic circuits including non-binary arithmetic circuits. By using CTDs, one can describe and analyze arbitrary adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures considered in this paper include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also presents an application of CTDs to the design of fast adders with limited carry propagation. A possibility of CTD-based synthesis of arithmetic circuits is suggested.

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