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A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference
Ryota Kayanoma, Akira Jinguji and Hiroki Nakahara
Machine learning is expanding in various applications, such as image processing in data centers. With the spread of deep learning, neural-network-based models have frequently been adopted in recent years. Due to the slow processing speed of machine learning evaluation on a CPU, high-speed, dedicated hardware accelerators are often used. In particular, the demand for hardware accelerators in data centers is increasing, with a need for low power consumption and high-speed processing in a limited space. A lut-based ternary neural network has been proposed that is small and fast, but has a problem of degrading recognition accuracy due to quantization and pruning. We propose an ensemble ternary neural network. By increasing the number of ensembles, we have achieved recognition accuracy higher than that of models with fp32 weights and features.
Keywords: Field programmable gate array, ensemble, ternary neural network, neural network, artificial intelligence, image processing