Special Issue to Recognize T. Higuchi’s Contributions to Multiple-Valued VLSI Computing
Guest Editors
M. Kameyama, T. Hanyu, and T. Aoki
p. 407-436
Multiple-Valued Logic as a New Computing Paradigm – A Brief Survey of Higuchi’s Researchon Multiple-Valued Logic
Michitaka Kameyama, Takahiro Hanyu and Takafumi Aoki
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p. 437-465
Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams
Shinobu Nagayama, Alan Mischenko, Tsutomo Sasao and Jon T. Butler
Abstract
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p. 467-479
Four-Valued Magnetic Random Access Memory Based on Magneto Tunnel Junction and Resonant Tunneling Diode
Tetsuya Uemura and Masafumi Yamamoto
Abstract
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p. 481-497
Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic
Akira Mochizuki, Takahiro Hanyu and Michitaka Kameyama
Abstract
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p. 499-517
Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits
Tomohiro Takahashi and Takahiro Hanyu
Abstract
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p. 519-544
Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis
Masanori Natsui, Naofumi Homma, Takafumi Aoki, and Tatsuo Higuchi
Abstract
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p. 545-565
Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic – Device Scaling and Future Prospects
Katsuhiko Degawa, Takafumi Aoki, and Tatsuo Higuchi
Abstract
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p. 567-602
Terary GFSOP Minimization Using Kronecker Decision Diagrams and Their Synthesis with Quantum Cascades
Mozammel H.A. Khan,Marek A. Perkowski, Mujibur R. Khan and Pawel Kerntopf
Abstract
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p. 603-618
Intra/Inter-Chip CDMA Communications for Efficient Data Transmission Towards New Paradigm of Computing
Yasushi Yuminaka
Abstract
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p. 619-632
Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic
Takahiro Hanyu, Shunichi Kaeriyama and Michitaka Kameyama
Abstract
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