JAPED Home • Issue Contents

p. 13-23
Design and Performance Analysis of Low-Power Hybrid Full Adder Circuit
Rahul Mani Upadhyay and Manish Kumar
Abstract
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p. 25-32
Ladder Based High Pass Filter Using VDTA
Praween Kumar Sinha, Mudit Garg and Neelam Sharma
Abstract
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p. 33-49
Switched-Capacitor Equivalent of Some Active-RC Filters and a Novel Circuit
Sudhanshu Maheshwari and Iqbal A. Khan
Abstract
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p. 51-59
Implementation of High-Gain Low-Power Two Stage CMOS OP-AMP Employing Current Buffer Compensation in Nanoscale Regime
Pragati Gupta and Shyam Akashe
Abstract
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p. 61-69
Power Efficient LCR Dual Keeper Domino Logic Circuit
Manish Deo and Manish Kumar
Abstract
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p. 71-81
Tuning Approach Applied for New Band-pass Filter Circuit
Masroor Jahan and Sudhanshu Maheshwari
Abstract
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